On June 24, 2026, OpenAI and Broadcom jointly unveiled Jalapeño, OpenAI's first Intelligence Processor, at a formal ceremony in which Broadcom President and CEO Hock Tan and Semiconductor Solutions President Charlie Kawwas delivered the chip to OpenAI CEO Sam Altman and President Greg Brockman. The delivery of a physical sample was the headline event; the partnership itself had been announced in October 2025, when the two companies disclosed a strategic collaboration to deploy 10 gigawatts of OpenAI-designed AI accelerators through the second half of the decade.

The timeline from partnership announcement to chip delivery is important context. The October 2025 announcement committed to rack deployment starting in the second half of 2026 and completing by the end of 2029. Jalapeño is the first chip in that roadmap, representing the initial deliverable in an eight-year infrastructure program that was publicly committed to eight months before the chip appeared.

OpenAI calls Jalapeño its first custom Intelligence Processor, designed from scratch for LLM inference. The chip moved from design to manufacturing tape-out in approximately nine months, described by the companies as potentially the fastest high-performance ASIC development cycle ever achieved. OpenAI President Greg Brockman told CNBC that OpenAI's own AI models assisted substantially in the design process, noting that the degree to which their models were able to accelerate the pipeline was surprising to the team.

What Jalapeño Actually Is: The Architecture Argument

Jalapeño's architecture was designed around the kernels, memory movement, networking, and serving patterns that matter most for frontier AI models, rather than the broad range of workloads a general-purpose GPU must support. The chip reduces data movement and achieves near-theoretical peak utilization, closing the efficiency gap that wastes compute on conventional GPUs.

General-purpose GPUs are designed to handle diverse workloads efficiently across a wide range of applications. That generality requires architectural overhead: memory hierarchies, scheduling logic, and interconnect architectures that accommodate workloads the chip's designers cannot fully anticipate. An inference-optimized ASIC, by contrast, can be designed around the specific memory access patterns, batch sizes, and precision requirements of a known model class (in OpenAI's case, the transformer-based architectures that power every ChatGPT response).

Tom's Hardware described Jalapeño as a massive reticle-sized ASIC, meaning the compute chiplet measures approximately 840 $\text{mm}^2$, occupying nearly the maximum area that can be produced in a single EUV lithography exposure field (858 $\text{mm}^2$). Reticle-sized designs maximize compute density per chip but require extraordinary manufacturing precision and yield management. TSMC's involvement as fabricator and Broadcom's experience with yield optimization across its own chip portfolio are what make this scale feasible.

Richard Ho, who leads OpenAI's hardware program, stated that the team optimized the architecture around the kernels, memory movement, networking, and serving patterns that matter most for frontier AI models, enabling Jalapeño to execute core workloads close to the hardware's theoretical limits. Early engineering samples are running OpenAI's GPT-5.3-Codex-Spark model in the lab at target frequency and power levels, with a full technical report containing detailed benchmarks expected in the coming months.

The Microsoft Guarantee: Deployment and Commercial Structure

Initial reports stated that Jalapeño would be used exclusively within OpenAI's own infrastructure rather than sold commercially. However, the commercial deployment mechanism involves key partner integrations:

Microsoft is expected to purchase roughly 40% of initial Jalapeño production for its data centers. Jalapeño's first production deployment will be at gigawatt scale, populating AI data centers drawing a gigawatt or more of power with Jalapeño-based inference clusters. Microsoft has been confirmed as a primary deployment partner, with reports indicating that Broadcom required Microsoft to guarantee it will purchase 40% of the first production run to secure the initial deployment phase, a significant commercial commitment that underscores the scale of infrastructure investment behind the chip.

      OpenAI (Architecture & Model Design)
                       │
                       ▼
      Broadcom (ASIC Implementation & Networking)
                       │
                       ▼
      TSMC (Fabrication) ──► Celestica (Rack Integration)
                                       │
                                       ▼
                       Microsoft Azure (40% Guaranteed Offtake)

Jalapeño is not a chip OpenAI will sell freely in the open market; it is a chip whose inference capacity will be deployed inside Microsoft Azure, where OpenAI's models run for enterprise customers through the Azure OpenAI Service. The 40% Microsoft purchase guarantee is the mechanism that made the initial production commitment economically viable for Broadcom, reflecting the degree to which the OpenAI-Microsoft relationship governs infrastructure decisions across both organizations.

The Ramp Timeline

Broadcom CEO Hock Tan provided specific guidance to CNBC on the day of the announcement regarding the deployment rollout:

Tan stated that there would be "small prototype development" in late 2026, with scaling following that initial phase. He noted that the ramp would accelerate into 2027 and reach full capacity in the first half of 2028.

The practical reading of Tan's guidance points to prototype clusters in late 2026, meaningful inference workloads in 2027, and full production-scale deployment by mid-2028. The 10-gigawatt buildout commitment runs through the end of 2029, which implies multiple successive chip generations rather than a single prolonged deployment of Jalapeño specifically.

OpenAI's official announcement described Jalapeño as the first step in a multi-generation compute platform designed for initial deployment by the end of 2026 and expanding in the years ahead, combining OpenAI-designed accelerators with Broadcom silicon implementation, networking, and connectivity technologies, along with Celestica's board, rack, and system expertise.

The supply chain structure spans four distinct layers:

Architecture: OpenAI designs the accelerator architecture and model logic.
Implementation & Networking: Broadcom provides silicon implementation, Tomahawk networking, and interconnects.
Integration: Celestica integrates chips into production rack systems.
Fabrication: TSMC manufactures the physical wafers.

Strategic Implications for Nvidia and the ASIC Market

Nvidia shares fell roughly 1% on the day of the announcement, while Broadcom was flat. That market movement reflects a calibrated read of the near-term revenue threat: Jalapeño does not ship at scale until 2027–2028, and even at full deployment, it serves OpenAI's internal inference workload rather than competing in the open accelerator market.

The structural impact on Nvidia is longer-term:

Inference Shift: Every major AI customer that builds a custom inference ASIC reduces its reliance on general-purpose Nvidia GPUs for that specific workload. Google's TPUs, Amazon's Inferentia, Meta's MTIA, and now Jalapeño each represent a slice of inference workload that has been vertically integrated.
Training Moat: Nvidia's durable advantage remains in model training. The scale and complexity of frontier model training (with variable memory access patterns, irregular compute graphs, and evolving architectural requirements) continues to favor general-purpose GPUs over fixed-function ASICs.
Specialized Optimization: The inference market is where ASICs excel: the model architecture is fixed, the workload parameters are known, and the optimization surface is well-defined.

Broadcom's Position in Custom Silicon

For Broadcom, the deal validates its position as a primary ASIC design partner for hyperscalers building custom AI processors, a business that has contributed to a 44% gain in its stock over the past year.

Broadcom's custom silicon business has expanded substantially since 2023. Its relationships with Google (TPUs), Meta (MTIA), and now OpenAI place it at the center of the AI hardware ecosystem's vertical integration wave. Unlike Nvidia, which designs and markets a single chip architecture to all customers, Broadcom's model is to provide design services, networking silicon, and manufacturing coordination to customers who want to own their compute architecture.

Broadcom also supplies Meta with custom silicon through 2029, while Google has reportedly booked Intel for packaging over 3 million TPUs in 2028, illustrating the scale of the custom AI ASIC ecosystem forming around Broadcom and its manufacturing partners.

Full-Stack Infrastructure Ambitions

Greg Brockman's framing that "the world is moving to a compute-powered economy" and positioning Jalapeño as part of OpenAI's "long-term full-stack infrastructure strategy" outlines an ambition that extends beyond a single chip.

                  OPENAI FULL-STACK CONTROL
┌─────────────────────────┬────────────────────────────────────────┐
│ Layer                   │ Current Implementation                 │
├─────────────────────────┼────────────────────────────────────────┤
│ Model & Software        │ GPT-5 series / ChatGPT / API           │
│ Inference Silicon       │ Jalapeño (Broadcom / TSMC)             │
│ Data Center Infrastructure│ Stargate / Azure / 10 GW Program     │
│ Training Silicon        │ Nvidia GPUs (Primary Dependency)       │
└─────────────────────────┴────────────────────────────────────────┘

The primary remaining gap in that stack is training silicon, which remains dependent on Nvidia GPUs. Whether OpenAI's multi-generation roadmap eventually expands into custom training accelerators remains an open question, but Jalapeño addresses the area where OpenAI's immediate operational volume and cost pressures are highest: inference.

Compressing the Semiconductor Design Cycle

The nine-month design-to-tape-out timeline represents a notable shift in semiconductor development workflows. Traditional high-performance ASIC development cycles typically run 18 to 36 months. Compressing that cycle to nine months using AI-assisted design tools and tight software-hardware co-development changes the economics of custom silicon.

If a nine-month cycle proves repeatable, successive Jalapeño generations could incorporate architectural adjustments from production model deployments at a pace that matches or exceeds traditional GPU hardware refresh cycles. An AI lab that can design and tape out custom inference silicon in nine months can align its hardware iterations directly with its model updates, creating a feedback loop between model software and physical hardware.

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